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1 From 4a142cb2a68dc279aa90f1850c4af363b29f02e7 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
3 Date: Tue, 11 Mar 2025 15:13:45 -0300
4 Subject: [PATCH] drm/v3d: Associate a V3D tech revision to all supported
5 devices
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 The V3D driver currently determines the GPU tech version (33, 41...)
11 by reading a register. This approach has worked so far since this
12 information wasn’t needed before powering on the GPU.
13
14 V3D 7.1 introduces new registers that must be written to power on the
15 GPU, requiring us to know the V3D version beforehand. To address this,
16 associate each supported SoC with the corresponding VideoCore GPU version
17 as part of the device data.
18
19 To prevent possible mistakes, add an assertion to verify that the version
20 specified in the device data matches the one reported by the hardware.
21 If there is a mismatch, the kernel will trigger a warning.
22
23 Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
24 Signed-off-by: Maíra Canal <mcanal@igalia.com>
25 ---
26 drivers/gpu/drm/v3d/v3d_debugfs.c | 126 +++++++++++++++---------------
27 drivers/gpu/drm/v3d/v3d_drv.c | 60 ++++++++++++--
28 drivers/gpu/drm/v3d/v3d_drv.h | 11 ++-
29 drivers/gpu/drm/v3d/v3d_gem.c | 10 +--
30 drivers/gpu/drm/v3d/v3d_irq.c | 6 +-
31 drivers/gpu/drm/v3d/v3d_perfmon.c | 4 +-
32 drivers/gpu/drm/v3d/v3d_sched.c | 6 +-
33 7 files changed, 138 insertions(+), 85 deletions(-)
34
35 --- a/drivers/gpu/drm/v3d/v3d_debugfs.c
36 +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
37 @@ -21,74 +21,74 @@ struct v3d_reg_def {
38 };
39
40 static const struct v3d_reg_def v3d_hub_reg_defs[] = {
41 - REGDEF(33, 42, V3D_HUB_AXICFG),
42 - REGDEF(33, 71, V3D_HUB_UIFCFG),
43 - REGDEF(33, 71, V3D_HUB_IDENT0),
44 - REGDEF(33, 71, V3D_HUB_IDENT1),
45 - REGDEF(33, 71, V3D_HUB_IDENT2),
46 - REGDEF(33, 71, V3D_HUB_IDENT3),
47 - REGDEF(33, 71, V3D_HUB_INT_STS),
48 - REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
49 -
50 - REGDEF(33, 71, V3D_MMU_CTL),
51 - REGDEF(33, 71, V3D_MMU_VIO_ADDR),
52 - REGDEF(33, 71, V3D_MMU_VIO_ID),
53 - REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
54 -
55 - REGDEF(71, 71, V3D_GMP_STATUS(71)),
56 - REGDEF(71, 71, V3D_GMP_CFG(71)),
57 - REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
58 + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
59 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
60 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
61 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
62 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
63 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
64 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
65 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),
66 +
67 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
68 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
69 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
70 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),
71 +
72 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)),
73 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)),
74 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)),
75 };
76
77 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
78 - REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
79 - REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
80 + REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
81 + REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
82 };
83
84 static const struct v3d_reg_def v3d_core_reg_defs[] = {
85 - REGDEF(33, 71, V3D_CTL_IDENT0),
86 - REGDEF(33, 71, V3D_CTL_IDENT1),
87 - REGDEF(33, 71, V3D_CTL_IDENT2),
88 - REGDEF(33, 71, V3D_CTL_MISCCFG),
89 - REGDEF(33, 71, V3D_CTL_INT_STS),
90 - REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
91 - REGDEF(33, 71, V3D_CLE_CT0CS),
92 - REGDEF(33, 71, V3D_CLE_CT0CA),
93 - REGDEF(33, 71, V3D_CLE_CT0EA),
94 - REGDEF(33, 71, V3D_CLE_CT1CS),
95 - REGDEF(33, 71, V3D_CLE_CT1CA),
96 - REGDEF(33, 71, V3D_CLE_CT1EA),
97 -
98 - REGDEF(33, 71, V3D_PTB_BPCA),
99 - REGDEF(33, 71, V3D_PTB_BPCS),
100 -
101 - REGDEF(33, 42, V3D_GMP_STATUS(33)),
102 - REGDEF(33, 42, V3D_GMP_CFG(33)),
103 - REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
104 -
105 - REGDEF(33, 71, V3D_ERR_FDBGO),
106 - REGDEF(33, 71, V3D_ERR_FDBGB),
107 - REGDEF(33, 71, V3D_ERR_FDBGS),
108 - REGDEF(33, 71, V3D_ERR_STAT),
109 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
110 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
111 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
112 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
113 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
114 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
115 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
116 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
117 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
118 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
119 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
120 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),
121 +
122 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
123 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),
124 +
125 + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)),
126 + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)),
127 + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)),
128 +
129 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
130 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
131 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
132 + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
133 };
134
135 static const struct v3d_reg_def v3d_csd_reg_defs[] = {
136 - REGDEF(41, 71, V3D_CSD_STATUS),
137 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
138 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
139 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
140 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
141 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
142 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
143 - REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
144 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
145 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
146 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
147 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
148 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
149 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
150 - REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
151 - REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
152 + REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
153 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)),
154 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)),
155 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)),
156 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)),
157 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)),
158 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)),
159 + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)),
160 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)),
161 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)),
162 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)),
163 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)),
164 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)),
165 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)),
166 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)),
167 + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
168 };
169
170 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
171 @@ -164,7 +164,7 @@ static int v3d_v3d_debugfs_ident(struct
172 str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
173 seq_printf(m, "TFU: %s\n",
174 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
175 - if (v3d->ver <= 42) {
176 + if (v3d->ver <= V3D_GEN_42) {
177 seq_printf(m, "TSY: %s\n",
178 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
179 }
180 @@ -196,11 +196,11 @@ static int v3d_v3d_debugfs_ident(struct
181 seq_printf(m, " QPUs: %d\n", nslc * qups);
182 seq_printf(m, " Semaphores: %d\n",
183 V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
184 - if (v3d->ver <= 42) {
185 + if (v3d->ver <= V3D_GEN_42) {
186 seq_printf(m, " BCG int: %d\n",
187 (ident2 & V3D_IDENT2_BCG_INT) != 0);
188 }
189 - if (v3d->ver < 40) {
190 + if (v3d->ver < V3D_GEN_41) {
191 seq_printf(m, " Override TMU: %d\n",
192 (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
193 }
194 @@ -234,7 +234,7 @@ static int v3d_measure_clock(struct seq_
195 int core = 0;
196 int measure_ms = 1000;
197
198 - if (v3d->ver >= 40) {
199 + if (v3d->ver >= V3D_GEN_41) {
200 int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
201 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
202 V3D_SET_FIELD_VER(cycle_count_reg,
203 --- a/drivers/gpu/drm/v3d/v3d_drv.c
204 +++ b/drivers/gpu/drm/v3d/v3d_drv.c
205 @@ -97,7 +97,7 @@ static int v3d_get_param_ioctl(struct dr
206 args->value = 1;
207 return 0;
208 case DRM_V3D_PARAM_SUPPORTS_PERFMON:
209 - args->value = (v3d->ver >= 40);
210 + args->value = (v3d->ver >= V3D_GEN_41);
211 return 0;
212 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
213 args->value = 1;
214 @@ -260,15 +260,44 @@ static const struct drm_driver v3d_drm_d
215 };
216
217 static const struct of_device_id v3d_of_match[] = {
218 - { .compatible = "brcm,2712-v3d" },
219 - { .compatible = "brcm,2711-v3d" },
220 - { .compatible = "brcm,2712-v3d" },
221 - { .compatible = "brcm,7268-v3d" },
222 - { .compatible = "brcm,7278-v3d" },
223 + { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 },
224 + { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 },
225 + { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 },
226 + { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 },
227 {},
228 };
229 MODULE_DEVICE_TABLE(of, v3d_of_match);
230
231 +static void
232 +v3d_idle_sms(struct v3d_dev *v3d)
233 +{
234 + if (v3d->ver < V3D_GEN_71)
235 + return;
236 +
237 + V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF);
238 +
239 + if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
240 + V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) {
241 + DRM_ERROR("Failed to power up SMS\n");
242 + }
243 +
244 + v3d_reset_sms(v3d);
245 +}
246 +
247 +static void
248 +v3d_power_off_sms(struct v3d_dev *v3d)
249 +{
250 + if (v3d->ver < V3D_GEN_71)
251 + return;
252 +
253 + V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF);
254 +
255 + if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
256 + V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) {
257 + DRM_ERROR("Failed to power off SMS\n");
258 + }
259 +}
260 +
261 static int
262 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
263 {
264 @@ -283,6 +312,7 @@ static int v3d_platform_drm_probe(struct
265 struct device_node *node;
266 struct drm_device *drm;
267 struct v3d_dev *v3d;
268 + enum v3d_gen gen;
269 int ret;
270 u32 mmu_debug;
271 u32 ident1, ident3;
272 @@ -296,6 +326,9 @@ static int v3d_platform_drm_probe(struct
273
274 platform_set_drvdata(pdev, drm);
275
276 + gen = (enum v3d_gen)of_device_get_match_data(dev);
277 + v3d->ver = gen;
278 +
279 ret = map_regs(v3d, &v3d->hub_regs, "hub");
280 if (ret)
281 return ret;
282 @@ -304,6 +337,12 @@ static int v3d_platform_drm_probe(struct
283 if (ret)
284 return ret;
285
286 + if (v3d->ver >= V3D_GEN_71) {
287 + ret = map_regs(v3d, &v3d->sms_regs, "sms");
288 + if (ret)
289 + return ret;
290 + }
291 +
292 v3d->clk = devm_clk_get_optional(dev, NULL);
293 if (IS_ERR(v3d->clk))
294 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
295 @@ -314,6 +353,8 @@ static int v3d_platform_drm_probe(struct
296 return ret;
297 }
298
299 + v3d_idle_sms(v3d);
300 +
301 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
302 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
303 ret = dma_set_mask_and_coherent(dev, mask);
304 @@ -325,6 +366,11 @@ static int v3d_platform_drm_probe(struct
305 ident1 = V3D_READ(V3D_HUB_IDENT1);
306 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
307 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
308 + /* Make sure that the V3D tech version retrieved from the HW is equal
309 + * to the one advertised by the device tree.
310 + */
311 + WARN_ON(v3d->ver != gen);
312 +
313 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
314 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
315
316 @@ -377,7 +423,7 @@ static int v3d_platform_drm_probe(struct
317 v3d->clk_down_rate =
318 (clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;
319
320 - if (v3d->ver < 41) {
321 + if (v3d->ver < V3D_GEN_41) {
322 ret = map_regs(v3d, &v3d->gca_regs, "gca");
323 if (ret)
324 goto clk_disable;
325 --- a/drivers/gpu/drm/v3d/v3d_drv.h
326 +++ b/drivers/gpu/drm/v3d/v3d_drv.h
327 @@ -94,11 +94,18 @@ struct v3d_perfmon {
328 u64 values[] __counted_by(ncounters);
329 };
330
331 +enum v3d_gen {
332 + V3D_GEN_33 = 33,
333 + V3D_GEN_41 = 41,
334 + V3D_GEN_42 = 42,
335 + V3D_GEN_71 = 71,
336 +};
337 +
338 struct v3d_dev {
339 struct drm_device drm;
340
341 /* Short representation (e.g. 33, 41) of the V3D tech version */
342 - int ver;
343 + enum v3d_gen ver;
344
345 /* Short representation (e.g. 5, 6) of the V3D tech revision */
346 int rev;
347 @@ -205,7 +212,7 @@ to_v3d_dev(struct drm_device *dev)
348 static inline bool
349 v3d_has_csd(struct v3d_dev *v3d)
350 {
351 - return v3d->ver >= 41;
352 + return v3d->ver >= V3D_GEN_41;
353 }
354
355 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
356 --- a/drivers/gpu/drm/v3d/v3d_gem.c
357 +++ b/drivers/gpu/drm/v3d/v3d_gem.c
358 @@ -26,7 +26,7 @@ v3d_init_core(struct v3d_dev *v3d, int c
359 * type. If you want the default behavior, you can still put
360 * "2" in the indirect texture state's output_type field.
361 */
362 - if (v3d->ver < 40)
363 + if (v3d->ver < V3D_GEN_41)
364 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
365
366 /* Whenever we flush the L2T cache, we always want to flush
367 @@ -59,7 +59,7 @@ v3d_idle_axi(struct v3d_dev *v3d, int co
368 static void
369 v3d_idle_gca(struct v3d_dev *v3d)
370 {
371 - if (v3d->ver >= 41)
372 + if (v3d->ver >= V3D_GEN_41)
373 return;
374
375 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
376 @@ -133,13 +133,13 @@ v3d_reset(struct v3d_dev *v3d)
377 static void
378 v3d_flush_l3(struct v3d_dev *v3d)
379 {
380 - if (v3d->ver < 41) {
381 + if (v3d->ver < V3D_GEN_41) {
382 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
383
384 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
385 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
386
387 - if (v3d->ver < 33) {
388 + if (v3d->ver < V3D_GEN_33) {
389 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
390 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
391 }
392 @@ -152,7 +152,7 @@ v3d_flush_l3(struct v3d_dev *v3d)
393 static void
394 v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
395 {
396 - if (v3d->ver > 32)
397 + if (v3d->ver >= V3D_GEN_33)
398 return;
399
400 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
401 --- a/drivers/gpu/drm/v3d/v3d_irq.c
402 +++ b/drivers/gpu/drm/v3d/v3d_irq.c
403 @@ -143,7 +143,7 @@ v3d_irq(int irq, void *arg)
404 /* We shouldn't be triggering these if we have GMP in
405 * always-allowed mode.
406 */
407 - if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
408 + if (v3d->ver < V3D_GEN_71 && (intsts & V3D_INT_GMPV))
409 dev_err(v3d->drm.dev, "GMP violation\n");
410
411 /* V3D 4.2 wires the hub and core IRQs together, so if we &
412 @@ -201,7 +201,7 @@ v3d_hub_irq(int irq, void *arg)
413
414 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
415
416 - if (v3d->ver >= 41) {
417 + if (v3d->ver >= V3D_GEN_41) {
418 axi_id = axi_id >> 5;
419 if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
420 client = v3d41_axi_ids[axi_id];
421 @@ -220,7 +220,7 @@ v3d_hub_irq(int irq, void *arg)
422 status = IRQ_HANDLED;
423 }
424
425 - if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
426 + if (v3d->ver >= V3D_GEN_71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
427 dev_err(v3d->drm.dev, "GMP Violation\n");
428 status = IRQ_HANDLED;
429 }
430 --- a/drivers/gpu/drm/v3d/v3d_perfmon.c
431 +++ b/drivers/gpu/drm/v3d/v3d_perfmon.c
432 @@ -200,10 +200,10 @@ void v3d_perfmon_init(struct v3d_dev *v3
433 const struct v3d_perf_counter_desc *counters = NULL;
434 unsigned int max = 0;
435
436 - if (v3d->ver >= 71) {
437 + if (v3d->ver >= V3D_GEN_71) {
438 counters = v3d_v71_performance_counters;
439 max = ARRAY_SIZE(v3d_v71_performance_counters);
440 - } else if (v3d->ver >= 42) {
441 + } else if (v3d->ver >= V3D_GEN_42) {
442 counters = v3d_v42_performance_counters;
443 max = ARRAY_SIZE(v3d_v42_performance_counters);
444 }
445 --- a/drivers/gpu/drm/v3d/v3d_sched.c
446 +++ b/drivers/gpu/drm/v3d/v3d_sched.c
447 @@ -361,11 +361,11 @@ v3d_tfu_job_run(struct drm_sched_job *sc
448 V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica);
449 V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua);
450 V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa);
451 - if (v3d->ver >= 71)
452 + if (v3d->ver >= V3D_GEN_71)
453 V3D_WRITE(V3D_V7_TFU_IOC, job->args.v71.ioc);
454 V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios);
455 V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]);
456 - if (v3d->ver >= 71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
457 + if (v3d->ver >= V3D_GEN_71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
458 V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]);
459 V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]);
460 V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]);
461 @@ -416,7 +416,7 @@ v3d_csd_job_run(struct drm_sched_job *sc
462 *
463 * XXX: Set the CFG7 register
464 */
465 - if (v3d->ver >= 71)
466 + if (v3d->ver >= V3D_GEN_71)
467 V3D_CORE_WRITE(0, V3D_V7_CSD_QUEUED_CFG7, 0);
468
469 /* CFG0 write kicks off the job. */
OpenWrt Source Repository